This invention relates to a semiconductor pattern mask having features to minimize aberrations. More particularly, this invention relates to a semiconductor pattern mask having sub-resolution features to reduce the sensitivity of the pattern to aberrations in the optics of the pattern imaging system.
Semiconductor devices are typically manufactured using photolithographic techniques. The circuit elements or structures to be formed are drawn on a mask. The mask can be a “dark field layout” in which the circuit elements are represented by light-transmissive areas on a nontransmissive (or less transmissive) background, or a “clear field layout” in which the circuit elements are represented by nontransmissive (or less transmissive) areas on a transmissive background.
A silicon substrate, suitably doped, is provided with a photosensitive coating or “photoresist.” The photosensitive coating is exposed to light through the mask using an optical system, and is then processed to develop the circuit elements on the silicon substrate. The process is repeated for multiple layers of silicon and metallization (using a different mask for each layer) until the desired circuit has been formed.
The optical elements in the optical system used to expose the photosensitive surface through the mask may be imperfect. For example, lenses in that system may be manufactured with one of several optical aberrations.
One such aberration, known as three-leaf aberration, may cause distortion of the imaging of the mask features onto the photosensitive surface, resulting in corresponding distortions in the final semiconductor device.
It would be desirable to be able to provide a way to eliminate the sensitivity of semiconductor pattern mask to three-leaf aberration.